Some phase lock loops (“PLLs”) may be configured to have little phase noise, such as inductor-capacitor or “tank” circuit phase lock loops (“LC PLLs”) for example, at high frequencies of operation, such as in excess of 16 GHz for example. Such LC PLLs conventionally consume a significant amount of power and semiconductor die area. For such high frequency operation, it would be beneficial if input/output blocks, transceiver blocks, and other communication blocks could have a local PLL that has low power and low phase noise. However, such communication blocks conventionally are too numerous on a semiconductor die for each such communication block to have its own LC PLL, for reasons of power distribution and/or size limitations.
Accordingly, it would be both desirable and useful to provide a PLL with sufficiently low power and phase noise for widespread usage on a semiconductor die.